? semiconductor components industries, llc, 2011 june, 2011 ? rev. 10 1 publication order number: mc100ep210s/d mc100ep210s 2.5v?1:5 dual differential lvds compatible clock driver description the mc100ep210s is a low skew 1 ? to ? 5 dual differential driver, designed with lvds clock distribution in mind. the lvds or lvpecl input signals are differential and the signal is fanned out to five identical differential lvds outputs. the ep210s specifically guarantees low output ? to ? output skew. optimal design, layout, and processing minimize skew within a device and from device to device. two internal 50 resistors are provided across the inputs. for lvds inputs, vta and vtb pins should be unconnected. for lvpecl inputs, vta and vtb pins should be connected to the v tt (v cc ? 2.0 v) supply. designers can take advantage of the ep210s performance to distribute low skew lvds clocks across the backplane or the board. features ? 20 ps typical output ? to ? output skew ? 85 ps typical device ? to ? device skew ? 550 ps typical propagation delay ? the 100 series contains temperature compensation ? maximum frequency > 1 ghz typical ? operating range: v cc = 2.375 v to 2.625 v with v ee = 0 v ? internal 50 input termination resistors ? lvds input/output compatible ? these are pb ? free devices lqfp ? 32 fa suffix case 873a marking diagram* *for additional marking information, refer to application note and8002/d. http://onsemi.com mc100 ep210s awlyywwg see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information xxx = 10 or 100 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb ? free package 32 1 mcxxx ep210s alywg 1 qfn32 mn suffix case 488am
mc100ep210s http://onsemi.com 2 clkn, clkn lvds, lvpecl clk inputs* v cc 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 qb4 qb4 qb3 qb3 qb2 qb2 v cc v cc qa0 qa0 qa1 qa1 qa2 qa2 v cc v ee vtb v ee qb1 qb1 qb0 qb0 qa4 qa4 qa3 qa3 qa0 qa0 qa1 qa1 qa2 qa2 qa3 qa3 qa4 qa4 clka clka vta qb0 qb0 qb1 qb1 qb2 qb2 qb3 qb3 qb4 qb4 clkb clkb warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. table 1. pin description pin qn0:4, qn0:4 lvds outputs function v cc positive supply v ee ground figure 1. 32 ? lead lqfp pinout (top view) clka clka clkb clkb figure 2. logic diagram vta vtb vta 50 50 vtb 50 50 50 termination resistors 50 termination resistors mc100ep210s *under open or floating conditions with input pins converging to a common termination bias voltage the device is susceptible to auto oscillation. v cc 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 qb4 qb4 qb3 qb3 qb2 qb2 v cc v cc qa0 qa0 qa1 qa1 qa2 qa2 v cc v ee vtb v ee qb1 qb1 qb0 qb0 qa4 qa4 qa3 qa3 clka clka clkb clkb vta mc100ep210s figure 1. 32 ? lead qfn pinout (top view) the exposed pad (ep) on the qfn ? 32 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to v ee . ep for qfn ? 32, only
mc100ep210s http://onsemi.com 3 table 2. attributes characteristics value esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb ? free pkg lqfp ? 32 qfn ? 32 level 2 level 2 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 461 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, refer to application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc power supply v ee = 0 v 6 v v ee power supply (gnd) v cc = 2.5 v ? 6 v v i lvds, lvpecl input voltage v ee = 0 v v i v cc 6 v i out output current continuous surge 50 100 ma ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm 32 lqfp 32 lqfp 80 55 c/w c/w jc thermal resistance (junction ? to ? case) standard board 32 lqfp 12 to 17 c/w ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm qfn ? 32 qfn ? 32 31 27 c/w c/w jc thermal resistance (junction ? to ? case) 2s2p qfn ? 32 12 c/w t sol wave solder pb pb ? free 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
mc100ep210s http://onsemi.com 4 table 4. dc characteristics v cc = 2.5 v, v ee = 0 v (note 2) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 150 200 150 200 150 200 ma v oh output high voltage (note 3) 1250 1400 1550 1250 1400 1550 1250 1400 1550 mv v ol output low voltage (note 3) 800 950 1100 800 950 1100 800 950 1100 mv v ihcmr input high voltage common mode range (differential configuration) (note 4) 1.2 2.5 1.2 2.5 1.2 2.5 v r t internal termination resistor 43 57 43 50 57 43 57 i ih input high current 150 150 150 a i il input low current clk clk ? 150 ? 150 150 150 ? 150 ? 150 150 150 ? 150 ? 150 150 150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . 3. all loading with 100 across lvds differential outputs. 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 5. ac characteristics v cc = 2.375 to 2.625 v, v ee = 0 v (note 5) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f maxlvds/ lvpecl maximum frequency (see figure 2. f max /jitter) > 1 > 1 > 1 ghz t plh t phl propagation delay 425 525 625 450 550 650 475 575 675 ps t skew within ? device skew (note 6) device ? to ? device skew (note 7) duty cycle skew (note 8) 20 85 80 25 160 100 20 85 80 25 160 100 20 85 80 35 160 100 ps t jitter rms random clock jitter 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp minimum input swing 150 800 1200 150 800 1200 150 800 1200 mv t r /t f output rise/fall time (20% ? 80%) 50 130 200 75 150 225 80 160 230 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. measured with 400 mv source, 50% duty cycle clock source. all loading with 100 across differential outputs. 6. skew is measured between outputs under identical transitions of similar paths through a device. 7. device ? to ? device skew for identical transitions at identical v cc levels. 8. duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of t he output.
mc100ep210s http://onsemi.com 5 0 50 100 150 200 250 300 350 400 450 0 200 400 600 800 1000 1200 1400 figure 2. f max frequency (mhz) v outpp (mv) simulated driver device oscilloscope qd q d lvds 100 z o = 50 z o = 50 figure 3. typical termination for output driver and device evaluation hi z probe hi z probe
mc100ep210s http://onsemi.com 6 figure 4. tape and reel pin 1 quadrant orientation ordering information device package shipping ? mc100ep210sfag lqfp ? 32 (pb ? free) 250 units / tray mc100ep210sfar2g lqfp ? 32 (pb ? free) 2000 / tape & reel (pin 1 orientation in quadrant b, figure 4) MC100EP210SFATWG lqfp ? 32 (pb ? free) 2000 / tape & reel (pin 1 orientation in quadrant a, figure 4) mc100ep210smng qfn ? 32 (pb ? free) 72 units / tray mc100ep210smnr4g qfn ? 32 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc100ep210s http://onsemi.com 7 package dimensions 32 lead lqfp case 873a ? 02 issue c detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae ? ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ? t ? ? z ? ? u ? t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ? ac ? ? ab ? m 8x ? t ? , ? u ? , ? z ? t-u m 0.20 (0.008) z ac notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ? ab ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ? t ? , ? u ? , and ? z ? to be determined at datum plane ? ab ? . 5. dimensions s and v to be determined at seating plane ? ac ? . 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ? ab ? . 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
mc100ep210s http://onsemi.com 8 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc100ep2105/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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